30 September 2013 to 4 October 2013
US/Pacific timezone

The Spiral2 LLRF FPGA design applied to the control of the RFQ

Not scheduled


Mr Samuel Sube (CEA DSM IRFU) Mr Yannick MARIETTE (CEA)


CEA/Saclay developed the LLRF system to control the accelerator cavities of Spiral2. Its architecture, based on in-house VME64x boards equipped with a Virtex-5 FPGA, was described in the previous LLRF workshops. The FPGA VHDL/C developments follow a modular approach to build a generic design applicable to all the cavity types (RFQ, normal conducting rebunchers and superconducting resonators). The poster presents an overview of this design, split between a softcore µ-processor and VHDL modules, and how this organization provides the needed flexibility to configure the LLRF for the several cavity types. The emphasis is put on the RFQ control, which is the most complex because it is driven by four power amplifiers, and because it cannot be driven at fixed frequency during startup.

Primary author

Mr Samuel Sube (CEA DSM IRFU)


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