30 September 2013 to 4 October 2013
US/Pacific timezone

PCIe and VME low latency data transfer in scalable LLRF systems

Not scheduled


Mr Mario Jurcevic (Paul Scherrer Institut)


The design of a digital LLRF system for SwissFEL with repetition rate of 100 Hz and distributed ADC channels demands for a concept with high-speed and low latency data transfer links and a variable number of connected boards. The modular unit of digital part of the LLRF system is a VME board with PCI express based infrastructure between FPGA, CPU and external PCI express devices. Two FMC mezzanine slots are available for connection of ADC/DAC cards. Since feedback algorithms shall run on a central carrier board, where the DAC mezzanine card is located, the data transfer of all required ADC's has to be implemented in a flexible manner with lowest possible latency. Performance figures for latency values for different link types (VME bus, PCI express) as a function of data packet size are presented.

Primary author

Mr Mario Jurcevic (Paul Scherrer Institut)


Mr Alexander Dietrich (Paul Scherrer Institut) Mr Andreas Hauff (Paul Scherrer Institut) Mr Florian Gaertner (Paul Scherrer Institut) Mr Lionel Schebacher (Paul Scherrer Institut) Mr Roger Kalt (Paul Scherrer Institut) Dr Thomas Schilcher (Paul Scherrer Institut)

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