30 September 2013 to 4 October 2013
US/Pacific timezone

FMC ADC/DAC experiences for SwissFEL

Not scheduled
Poster

Speaker

Mr Roger Kalt (Paul Scherrer Institut)

Description

Modern digital LLRF control systems especially for pulsed machines demand multiple fast sampling and high precision data acquisition channels per RF station. The performance of such an acquisition channel is mainly limited by the used ADC/DAC type, clock distributor chips, and the layout and circuitry around these integrated circuits. With FMC (FPGA Mezzanine Card), a standardized form factor was made available in 2008 and it solves an essential design question of each digital board designer: Where to place ADC/DAC and FPGA chips and how to connect them? Due to standardized digital interface, FMC provides an easy and well defined upgrade path for ADC/DAC FMC mezzanines. This poster shows how PSI solves the integration issues of 800 high speed and high precision data acquisition channels for SwissFEL using FMC mezzanines. It deals with special aspects the designer should take care for optimal use of the FMC standard. Finally performance figures for evaluated ADC/DAC FMC mezzanines are presented.

Primary authors

Mr Florian Gärtner (Paul Scherrer Institut) Mr Lionel Schebacher (Paul Scherrer Institut) Mr Roger Kalt (Paul Scherrer Institut)

Co-authors

Mr Alexander Dietrich (Paul Scherrer Institut) Mr Andreas Hauff (Paul Scherrer Institut)

Presentation Materials

There are no materials yet.