Speaker
Mrs
Geetha Narayan
(BNL)
Description
The tutorial will demonstrate the integrated flow from system design to implementation of real-time DSP applications on FPGAs. The objective is to show developers with limited or no FPGA design experience that they can quickly take a DSP algorithm from concept to verification. Traditional RTL developers can also benefit from this design methodology to cut down on verification time and perform implementation trade-off analysis.
The steps taken to validate a simple application using XILINX System Generator with MATLAB / Simulink and hardware-in-loop verification will be shown. An overview of our current designs at BNL using this method and results achieved will be discussed.
Author
Mrs
Geetha Narayan
(BNL)
