Mrs
Geetha Narayan
(BNL)
02/10/2013, 10:40
Oral
The tutorial will demonstrate the integrated flow from system design to implementation of real-time DSP applications on FPGAs. The objective is to show developers with limited or no FPGA design experience that they can quickly take a DSP algorithm from concept to verification. Traditional RTL developers can also benefit from this design methodology to cut down on verification time and perform...
